A Checkfield signal is a special test signal that stresses particular aspects of serial digital transmission. The performance of the Phase Locked-Loops (PLLs) in an SDI receiver must be able to tolerate long runs of 0’s and 1’s. Under normal conditions, only very short runs of these are produced due to a scrambling algorithm that is used. The Checkfield, also referred to as the Pathological test signal, will “undo” the scrambling and cause extremely long runs to occur. This test signal is very useful for testing transmission paths.